Introduction: The Silicon Scaling Crisis
For over five decades, silicon transistors have powered the digital revolution. But as chip features shrink below 7 nanometers, silicon's diminishing returns threaten to stall computing progress. Enter indium gallium arsenide (InGaAs), a III-V compound semiconductor whose exceptional electron mobility—up to 50× faster than silicon—positions it as the leading candidate to extend Moore's Law into the next decade. Recent breakthroughs presented at the 2025 VLSI Symposium reveal how scientists are overcoming integration hurdles to unlock InGaAs' potential for next-generation CMOS technology 2 .
Electron Mobility
InGaAs offers electron mobility up to 50 times faster than silicon, enabling significantly higher performance at lower power.
Moore's Law Extension
As silicon approaches physical limits, InGaAs emerges as the most promising successor to continue transistor scaling.
Key Concepts: Why InGaAs?
1 The Speed Advantage
InGaAs' crystal structure enables electrons to zip through channels with minimal resistance. This translates to:
- Lower power consumption at high frequencies
- Higher drive currents for computational density
- Enhanced high-frequency performance (critical for 5G/6G and AI accelerators)
Did You Know?
InGaAs' electron velocity remains high even at nanoscale dimensions due to ballistic transport effects 2 .
2 The Scaling Paradox
While planar InGaAs MOSFETs have demonstrated record transconductance (3.45 mS/µm), their gate lengths struggle to drop below 40 nm. To transcend this, researchers pivoted to 3D architectures like finFETs—the same structures used in cutting-edge silicon nodes 2 .
FinFET Revolution
The transition to 3D finFET architectures has enabled InGaAs to overcome planar scaling limitations while maintaining performance advantages 2 .
3 Silicon Integration Imperative
The ultimate goal is monolithic integration of InGaAs channels on silicon wafers. Aeluma's recent demonstration of 200 mm CMOS-compatible InGaAs photodetectors proves large-scale manufacturing feasibility, bridging III-V performance with silicon's economies of scale 5 7 .
In Focus: MIT's Record-Breaking InGaAs FinFET Experiment
How researchers at MIT tamed fin defects and contact resistance to achieve unprecedented performance.
Methodology: The Dual-Step Fin Sculpting
1. Reactive Ion Etching
- BCl₃/SiCl₄/Ar plasma mixture
- Initial fin widths ~15 nm
- Sidewall roughness issues
2. Digital Etch Refinement
- 3+ cycles of atomic-scale sculpting
- Final fin width: 8 nm
- Aspect ratio >21
3. Contact Engineering
- Molybdenum contacts
- Contact resistivity: ~10⁻⁹ Ω·cm²
- Minimized signal loss
Results & Analysis: Closing the Gap with Silicon
Electron Mobility vs. Fin Width
| Fin Width (nm) | Electron Mobility (cm²/V·s) |
|---|---|
| 30 | 3,500 |
| 20 | 2,900 |
| 8 | 1,200 |
Mobility declined below 15 nm but remained superior to silicon. Critically, electron velocity (the true performance metric) stayed high due to ballistic transport 2 .
Transconductance Benchmarking
| Normalization Method | InGaAs finFET (MIT) | Si finFET (Intel 14nm) |
|---|---|---|
| By gate periphery | ~1.8 mS/µm | ~2.0 mS/µm |
| By fin width | 0.65 mS/µm | 1.2 mS/µm |
While trailing silicon in footprint-normalized metrics, MIT's devices set a 50% improvement over prior InGaAs finFETs—a pivotal leap toward competitiveness 2 .
Sidewall Interface Quality
The digital etch process slashed interface defects by 16×, enabling effective gate control 2 .
The Scientist's Toolkit: Key Research Reagents
| Material/Reagent | Function |
|---|---|
| In₀.₅₃Ga₀.₄₇As substrates | Matches InP lattice constant; optimal electron mobility |
| Molybdenum (Mo) | Low-resistivity ohmic contacts for source/drain regions |
| BCl₃/SiCl₄ plasma | Anisotropic etching of III-V fins with vertical sidewalls |
| Cyclic digital etchants | Atomic-scale fin width control and surface passivation |
| High-κ dielectrics | Al₂O₃/HfO₂ stacks for enhanced gate control with minimal leakage |
| 200-300mm Si wafers | CMOS-compatible substrates for heterogeneous integration (Aeluma's approach) 5 7 |
Beyond the Lab: Industry's Roadmap
Aeluma's upcoming presentations at CS Mantech 2025 and IEEE OIP 2025 will spotlight:
Quantum Dot Lasers
Monolithic quantum dot lasers for silicon photonics
SWIR Photodetectors
On 300mm silicon wafers for mass production
High-speed APDs
For optical interconnects in AI clusters 7
Simultaneously, Semiconductor Today reports massive investments in GaN-on-SiC and InP HBTs, confirming the industry's pivot toward compound semiconductors .
Conclusion: The Path to Commercialization
MIT's finFET breakthroughs and Aeluma's wafer-scale integration mark a watershed in the InGaAs revolution. As Dr. Jesús del Alamo (MIT) notes: "We're not just extending Moore's Law—we're enabling new synergies between logic, sensing, and quantum computing." Challenges remain in defect density and cost, but with prototypes already matching silicon's electrostatic control at 20 nm gates, InGaAs channels could enter high-volume production by 2030—powering everything from neuromorphic AI chips to ultra-sensitive LiDAR 2 7 .
Further Reading
Covered in Semiconductor Today's July 2025 issue: www.semiconductor-today.com
Timeline to Commercialization
2025
Lab-scale prototypes demonstrate viability
2027
First commercial test chips
2030
High-volume production expected