How Atomic-Level Precision is Forging the Future of Microchips
The secret to faster, more efficient electronics lies in depositing materials just one atom at a time.
Within every advanced microchip, a sprawling metropolis of microscopic wires, known as interconnects, ferries power and data between billions of transistors. For decades, this invisible infrastructure has been built from copper. But as we approach the frontier of the 2 nm node—where features are just a few atoms wide—copper is hitting its physical limits. Its resistance skyrockets, and it becomes prone to electromigration failures, a phenomenon where atomic displacement breaks the wire 3 5 .
The solution? A shift to a more robust metal, ruthenium (Ru), and a revolutionary manufacturing technique known as area-selective deposition (ASD). This powerful combination promises to extend Moore's Law further by enabling the creation of perfect, self-aligned ruthenium wires with atomic-scale precision, ensuring our devices can continue to become smaller, faster, and more efficient 1 7 .
Copper interconnects are manufactured using a "damascene" process, where trenches are carved into an insulator and filled with metal. However, copper requires bulky barrier layers to prevent it from diffusing into surrounding materials. At the 2 nm node, these barriers can consume over 60% of a wire's tiny volume, drastically increasing its overall resistance 5 8 .
As wire widths approach the electron mean free path of copper, scattering effects intensify, causing resistance to surge. This leads to excessive heat and unacceptable delays in signal transmission 3 .
Chipmakers have engineered remarkable stopgap solutions, such as ultra-thin cobalt liners and Ru-Co bilayers, to improve copper filling 5 . But these are merely temporary fixes.
Ruthenium emerges as the leading candidate to succeed copper, thanks to a suite of inherent advantages at the nanoscale:
| Property | Copper (Cu) | Ruthenium (Ru) | Advantage for Ru |
|---|---|---|---|
| Electron Mean Free Path | Relatively long | Shorter | Less resistivity increase when scaled |
| Electromigration Resistance | Lower | Higher | Improved reliability and chip lifetime |
| Diffusion Barrier Needed? | Yes | No | More conductor volume, lower resistance |
| Primary Process | Damascene (electroplating) | Semi-damascene/Subtractive Etch | Enables taller, higher-aspect-ratio lines |
Adopting ruthenium is only half the battle. The real breakthrough lies in how it's applied. This is where area-selective deposition (ASD) comes in—a "bottom-up" manufacturing paradigm that represents a radical departure from traditional "top-down" etching.
ASD is a precision-guided form of Atomic Layer Deposition (ALD). In standard ALD, a film grows uniformly over an entire surface through sequential, self-limiting chemical reactions 1 . ASD modifies this process by chemically engineering the surface beforehand.
The result is that ruthenium accumulates only on the pre-defined patterns, creating perfectly self-aligned wires without complex etching steps that can damage delicate nanostructures.
Substrate is patterned with dielectric and metal features. Creating an atomically clean and well-defined surface is crucial for successful deposition.
An inhibitor is applied to dielectric regions. The inhibitor must form a dense, defect-free layer to prevent unwanted deposition.
Ruthenium precursors are pulsed into the chamber. Precursors chemisorb and react only on metal regions, not on passivated dielectrics. Maintaining high selectivity is critical; even a few stray nuclei can cause a short circuit.
Inert gas purges excess precursor; a co-reactant is introduced. The co-reactant converts the adsorbed precursor into metallic ruthenium. Achieving a smooth, continuous film with low resistivity is essential.
Steps 3-4 are repeated to build the film to the desired thickness. The process must remain selective throughout all cycles to ensure perfect patterning.
While full subtractive etch of ruthenium is on the horizon, much of the current progress revolves around a hybrid technique called semi-damascene. This process was showcased in a landmark demonstration by researchers at imec, who achieved 16 nm pitch ruthenium lines with record-low resistance 6 .
Using extreme ultraviolet (EUV) lithography, narrow trenches are etched into a dielectric material.
A critical ASD step deposits a thin ruthenium seed layer selectively at the bottom and sides of these trenches. This ensures perfect alignment and continuity.
The trenches are then completely filled with more ruthenium using a technique like Chemical Vapor Deposition (CVD).
The wafer surface is polished flat, leaving behind perfectly formed, embedded ruthenium wires 6 .
The imec experiment yielded ruthenium interconnects with an average resistance of just 656 Ω/µm at a 16 nm pitch 6 . This result is significant because it proves that ruthenium, combined with advanced integration schemes like semi-damascene, can meet the stringent performance requirements for the A7 technology node and beyond. It demonstrates that the theoretical benefits of ruthenium—low resistance and scalability—can be translated into working, high-performance nanostructures.
| Material / Solution | Function | Role in Enabling 2 nm Node |
|---|---|---|
| Ruthenium (Ru) Precursors | Volatile compounds that carry Ru atoms in the gas phase for ALD/CVD. | The building block of the interconnect; its quality dictates the wire's resistivity and reliability. |
| Self-Assembled Monolayers (SAMs) | Molecular layers that form a dense, impermeable barrier on dielectric surfaces. | Act as the inhibitor in ASD, preventing Ru nucleation where it is not wanted and enabling self-alignment. |
| Trimethylaluminum (TMA) / Water | Common precursors for depositing Al₂O₃ by ALD. | Often used to create an initial "blocking layer" or to functionalize surfaces to enhance or suppress Ruthenium growth 1 . |
| Low-k / Ultra-Low-k Dielectrics | Insulating materials with a low dielectric constant (k). | Reduce capacitive crosstalk between adjacent wires, which is crucial for managing power consumption and signal speed. |
| Silicon Nitride (SiN) | A hard mask and etch stop layer. | Used as a core material in patterning processes to define the intricate shapes of the interconnects with high fidelity 7 . |
The path to widespread ruthenium adoption is not without hurdles. Maintaining perfect selectivity in ASD over many cycles is incredibly difficult; any small defect can lead to a short circuit. Furthermore, integrating ruthenium with air gaps (k ≈ 1.0) is a major focus to further reduce power-sapping capacitance, but this can compromise the mechanical stability of the chip 5 .
Despite these challenges, the industry is charging ahead. Major chipmakers like TSMC, Intel, and Samsung are deep in development, with imec's roadmap pointing to semi-damascene with air gaps as the future for the most advanced nodes 5 9 . The shift to ruthenium interconnects, enabled by the atomic-scale precision of area-selective deposition, is not just an incremental step—it is a fundamental transformation in how we build the backbone of our digital world. It ensures that the engine of the information age will continue to accelerate, powering everything from artificial intelligence to edge computing with unparalleled efficiency.